IIT Guwahati Develops Technology for Fast, Secure Computing

For faster and efficient computing the researchers at the Automation, Verification and Security (AVS) Lab at the Indian Institute of Technology  (IIT) Guwahati, have worked towards developing secure and dependable integrated circuits (ICs).

“With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs. While multicore processors are being used in modern times, their computing power improvements continue to be insufficient. To cite an analogy for better understanding, running more cars on the road does not necessarily mean you can reach your destination faster; in fact, more cars can lead to congestion and delays,” reads the press release by the institute.

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In this regard, the research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing ecosystem in our country, informed the institute.

The paper has been authored by Dr Chandan Karfa, associate professor, department of computer science & engineering, IIT Guwahati and co-authored his research students Mohammed Abderehman, Debebdara Senapati, Surajit Das, Priyanka Panigrahi and Nilotpola Sarma. Some alumni who contributed to these endeavours are Ramanuj Chouksey, Jay Oza, Yom Nigam, Abdul Khader and Jayprakash Patidar. The team has also collaborated with various international experts.

The findings have been published in top tier journals and conferences of IEEE. The research team is funded by ECR, CRG and Interdisciplinary Cyber-Physical Systems (ICPS) grants from the Department of Science & Technology, Govt. of India and by a Research Fellowship from Intel (India).

Pointing out the importance and need of research in the area of increasing computational power, Dr Chandan Karfa, said “A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualisation processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks.”

Further, Dr Chandan Karfa, said “We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features.”

In addition to these simulators, prototypes of which are available for testing, the IIT Guwahati team has also developed a technology called HOST, which protects Integrated Circuits from IP theft during the design cycle.

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